Appeal No. 2000-1361 Page 9
Application No. 08/933,880
registers 640 and 650, we find that these comparators indeed stop
multiplier 500 from generating any output value concurrent with
the enable signal sent to the output registers. In other words,
multiplier 500 is bypassed by sending a halt signal to the
multiplier in the event that a trivial operand is received from
input registers 640 and 650 at comparators 510-560. At the same
time, an enable signal is sent to the corresponding one of output
registers 570-630 causing them to sent their previously stored
values to register 670.
Based on the analysis above, we find that Richardson’s
enable signal is provided to the output registers if either
operand is trivial. Richardson has nothing to do with the time
at which an output value of the multiplier is present or
determining that time according to the value of the output of the
input registers. The output registers of Richardson provide to
register 670 the results that have been previously stored if the
comparators determine a trivial operand and send an enable signal
to the output registers. At the same time, a halt signal
prevents the operation of the multiplier. This condition is
different from the requirements of claim 1, in which the enable
signal is sent to the output register as soon as it is determined
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