Appeal No. 2002-0142
Application No. 09/248,957 Page 2
1. A flip-flop for asynchronous set and reset, comprising:
a first stage for inputting a differential set of data
inputs and generating a differential set of outputs;
a set and reset second stage for receiving said set of
differential set of outputs from said first stage and to output a
differential set of outputs including a Q signal and a Q signal
from said set and reset second stage, wherein said signal Q and
signal Q have equal delay times.
8. A flip-flop for asynchronous set and reset, comprising:
a first stage for inputting a differential set of data
inputs and generating a differential set of outputs, said outputs
being a set signal and a reset signal;
a set and reset second stage for receiving said set of
differential set of outputs from said first stage and to output a
differential set of outputs including a Q signal and a Q signal
from said set and reset second stage; and
a circuit to provide asynchronous operation of said set and
reset signals and to prevent short circuit connection when Set
and Clear 1are asserted.
The prior art reference of record relied upon by the
examiner in rejecting the appealed claims is:
Sato 5,532,634 July 2, 1996
Claims 1-8 stand rejected under 35 U.S.C. § 102(b) as being
anticipated by Sato.
1 Although we find no clear antecedent basis for "Set and Clear, because
the metes and bounds of the claim are readily understandable, we consider this
to be a formal matter that can be addressed by the examiner subsequent to the
appeal.
Page: Previous 1 2 3 4 5 6 7 8 9 10 Next
Last modified: November 3, 2007