Appeal No. 2002-0142
Application No. 09/248,957 Page 8
further discloses (col. 2, lines 30-39) that to achieve the
object of the invention, there is provided a J-K flip-flop
circuit having first and second flip-flop circuits constituted by
connecting inputs and outputs of two CMOS inverters to each
other, first NAND type connection means in which one end of three
MOS transistors, which respectively receive a first clock, a J
signal, and a signal from one node of the second flip-flop at
their gates, and have current paths connected in series with each
other. Sato further discloses (col. 2, lines 36-39) that one end
of the 3 MOS transistors:
is connected to one node of the first flip flop
circuit; second NAND type connection means in which one
end of three MOS transistors, which respectively
receive the first clock, a K signal, and a signal from
the other node of the second flip-flop circuit at their
gates, and have current paths connected in series with
each other, is connected to the other node of the first
flip-flop circuit.
The portions of Sato relied upon by the examiner to support the
examiner's assertion of asynchronous operation of the first
stage, as well as asynchronous set and reset functions are as
follows (col. 7, lines 18-25 and lines 45-52):
According to the arrangement shown in FIG. 5, when
the set signal S goes to “H”, the N-MOSFETs 35 and 36
are turned on, and the N-MOSFETs 37 and 38 are turned
off. Therefore, since the node 3 goes to “L”, the P-
MOSFET 13 is turned on, and the node 4 goes to “H”. On
the other hand, since the node 5 (BQ) goes to “L”, the
P-MOSFET 17 is turned on, and the node 6 (Q) goes to
“H”. In this manner, a set state is established.
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