Appeal No. 2002-0142
Application No. 09/248,957 Page 5
signals Q and Q are subject to the same delays. The examiner
alleges (answer, page 3 referring to the final rejection, paper
No. 8, and answer, pages 4, 6 and 7) that the time delay of the Q
signal in figure 7 of Sato is inherently equal to the time delay
of the Q signal because Sato's circuit has a symmetric structure.
Appellants argue (id.) that in figure 7 of Sato, "elements 29 and
44 are arranged significantly differently than elements 42 and
38. there is no symmetrical design and, consequently, no equal
delay times. Because of the different arrangement, there is no
inherency."
The examiner responds (answer, page 7) that since transistor
29 operates only during synchronous operation mode and
transistors 38, 42 and 44 only operate during asynchronous set
and reset mode, that appellants' arguments drawn to the symmetry
feature of these transistors is not a valid comparison.
From our review of Sato, we find no support for the
examiner's assertion that transistors 38, 42, and 44 operate in
asynchronous set and reset modes. We find that N-MOSFETS 35-38
were added to the embodiment of figure 3 to provide a set input
function to flip-flop circuits 1 and 2 (see figure 5, and col.
7., lines 1-5) and that N-MOSFETS 41-44 have been added in the
embodiment of figure 3 to provide a reset input function to the
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