Appeal No. 2002-0142
Application No. 09/248,957 Page 7
circuit is not asynchronous." The examiner responds (answer,
page 7) asserting:
However, Sato teaches on column 7, lines 18-25
that when the set signal S goes “H”, transistor 35 is
turned ON and transistor 37 is turned OFF, node 3(BP)
goes “L” and node 4(P) goes “H” regardless of the clock
signal CL2, i.e., the first stage is not dependent on
the next clock signal CL2 when the set signal S is
asserted (emphasis added).
On column 7, lines 45-52, Sato teaches when the reset
signal R goes “H”, transistor 41 is turned ON and transistor
43 is turned OFF, node 3(BP) goes “H” and node 4 (P) goes L”
regardless of the clock signal CL2, i.e., the first stage is
dependent on the next clock signal CL2 when the reset signal
is asserted (emphasis added).
From our review of Sato, we find that Sato discloses that in
prior art circuit arrangements, the J and K inputs are fetched by
the master flip-flop through an inverter operation in response to
clock pulses CP and BCP or a gate operation in response to the
clock pulses N1 and N2, and are shifted to the slave flip-flop to
obtain the outputs Q and BQ (col. 1, lines 48-54). Problems
associated with these circuits are that they result in a high
cost large scale integration (LSI), increased area of the
circuit, and these circuits are not suitable for high speed
operations (col. 1, line 55 through col. 2, line 6). It is an
object of the invention to reduce the number of elements in the
circuit, and to provide circuit means for supplying a logic
output of a control signal to a flip-flop circuit without using
any CMOS gate circuits (col. 2, lines 23-30 and 58-62). Sato
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