Appeal No. 2002-0142
Application No. 09/248,957 Page 9
According to the arrangement shown in FIG. 6, when
the reset signal R goes to “H”, the N-MOSFETs 41 and 42
are turned on, and the N-MOSFETs 43 and 44 are turned
off. Therefore, since the node 4 goes to “L”, the P-
MOSFET 11 is turned on, and the node 3 goes to “H”. On
the other hand, since the node 6 (Q) goes to “L”, the
P-MOSFET 15 is turned on, and the node 5 (BQ) goes to
“H”. Thus, a reset state is established.
From our review of Sato, we find no disclosure of Sato
teaching asynchronous operation of the first stage, or the set
and reset functions, as advanced by the examiner. The initial
burden of establishing a prima facie case rests with the
examiner. Here, the language of the portions of Sato relied upon
do not support the examiner's position as quoted, supra, and we
therefore agree with appellants that the operations of the
circuits of figures 6-8 of Sato are synchronous, i.e., clock
driven. Accordingly, we find that the examiner has failed to
establish a prima facie case of anticipation of independent claim
5. As the examiner (answer, pages 8 and 9) relies upon the same
portions of Sato for the other independent claims, we find that
the examiner has not established a prima facie case of
anticipation of claims 7 or 8. Accordingly, the rejection of
claims 1-8 under 35 U.S.C. § 102(b) as anticipated by Sato is
reversed.
CONCLUSION
Page: Previous 1 2 3 4 5 6 7 8 9 10 Next
Last modified: November 3, 2007