Appeal No. 2002-0142
Application No. 09/248,957 Page 6
flip-flop circuits 1 and 2 (see figure 6 and col. 7, lines 26-
29). We agree with appellants that as shown in figure 7,
referred to by the examiner, elements 29 and 44 are arranged
significantly differently than elements 42 and 38, and therefore
do not establish that signal Q and signal Q have equal delay
times. We are not persuaded by the examiner's (answer, pages 6
and 7) choosing from the circuit of figure 7, portions of the
circuit that also pertain to the circuit of figure 3, in an
attempt to read Sato on the claimed invention. In sum, we find
that the examiner has failed to point to any showing in Sato that
establishes equal delay times for the signals Q and Q. From all
of the above, we find that the examiner has failed to establish a
prima facie case of anticipation of claim 1. Accordingly, the
rejection of claim 1 under 35 U.S.C. § 102(b) is reversed.
We turn next to independent claims 5-8. The issue with
respect to these claims relates to a circuit to provide
asynchronous operation of the "first stage" (claim 5), "set
signal" (claim 6), "reset signal"(claim 7), and "set and reset"
signals (claim 8). Beginning with claim 5, appellant asserts
(brief, page 9) that inverters 40 and 45 and transistors 35, 37,
41, and 43, relied upon by the examiner (answer, page 5), are
dependent upon the next clock signal CL2, and consequently, the
Page: Previous 1 2 3 4 5 6 7 8 9 10 Next
Last modified: November 3, 2007