Appeal No. 2004-0633
Application No. 10/011,198
Appendix
31. A system of interconnects for a memory structure,
comprising:
a first interconnect within said memory structure;
a second interconnect coupled to said first interconnect
through a plug, wherein said second interconnect and said plug
define an integral structure;
a first insulator next to said second interconnect and said
plug, said first insulator having a height in at least one area
generally equal to a combined height of said second interconnect
and said plug; and
a second insulator next to said plug, said second insulator
having a height equal to a height of said plug.
32. The system in claim 31, wherein at least a portion of
said second interconnect is under said first interconnect.
33. The system in claim 32, wherein said portion of said
second interconnect is coupled to said first interconnect
through said plug.
34. A system of interconnects for a memory structure,
comprising:
a first interconnect within said memory structure; and
a second interconnect coupled to said first interconnect
through a plug, wherein said second interconnect and said plug
define an integral structure, wherein at least a portion of said
second interconnect is under said first interconnect, and
wherein said portion of said interconnects to coupled to
said first interconnect through said plug, and
a third interconnect laterally contacting a first insulator
and at least partially isolated from said first interconnect by
a second insulator.
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