Appeal No. 2004-0633
Application No. 10/011,198
a first conductive element on said first surface;
a second surface below said first surface; and
a second conductive element on said second surface, wherein
said second conductive element comprises a first part extending
to said first conductive element and a second part integral to
said first part and recessed from said first surface;
a first insulator lateral to said first part and said part
in a first area next to said second conductive element; and
a second insulator lateral to said first part in a second
area next to said second conductive element.
45. A memory device comprising:
a first surface of said memory device;
a first conductive element on said first surface;
a second surface below said first surface;
a second conductive element on said second surface, wherein
said second conductive element comprises a first part extending
to said first conductive element and a second part integral to
said first part and recessed from said first surface;
a first insulator lateral to said second conductive
element; and
a second insulator above said second part of said second
conductive element;
wherein a top of said first insulator and a top of said
second insulator define said first surface.
46. The memory device in claim 45, wherein said first
conductive element is a conductive line.
47. The memory device in claim 45, wherein said second
conductive element is an interconnect.
56. A multi-level circuit structure, comprising:
a first part of said circuit structure positioned in a
lower level of a memory device and isolated from a higher level
of said device; and
a second part of said circuit structure seamlessly coupled
to said first part, wherein said second part extends to said
higher level.
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