Appeal No. 2004-0633
Application No. 10/011,198
40. A level of interconnects for a semiconductor device,
comprising:
a layer of insulation defining a plurality of trenches
within said semiconductor device,
wherein each trench of said plurality defines a lower
portion and an upper portion, and
wherein:
said lower portion is filled with metal,
said metal extends up into at least one area of said upper
portion,
said upper portion is filled with oxide except in said at
least one area, and
said each trench is lined with a barrier layer.
41. The level of interconnects in claim 39, wherein said
each trench is lined with and adhesion layer.
42. A multi-layer interconnects structure for a memory
apparatus, comprising:
a first layer of insulation forming a part of said memory
apparatus;
a second layer of insulation over said first layer;
a first conductive path within said first layer of
insulation, wherein said first conductive path comprises a first
integral plug extending toward said second layer;
a discrete portion of insulation within said first layer,
over said first conductive path, and under said second layer of
insulation; and
a second conductive path within said second layer of
insulation, wherein said second conductive path contacts said
first plug.
43. The multi-layer interconnects structure of claim 42,
wherein said second layer of insulation has a top, and wherein
said second conductive path comprises a second integral plug
extending toward said top.
44. A memory device comprising:
a first surface of memory device;
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