Appeal 2006-1454
Application 09/004,524
Patent 5,483,421
a set of electrical connection sites formed on said circuit board and arranged
in a pattern corresponding to the pattern of the array of the second bonding pads on
said chip carrier;
a second set of solder connections interconnecting the pads of said second
set of bonding pads on the chip carrier to the connection sites on the circuit board;
and
wiring on said circuit board connected to said second set of bonding pads.
2. The package of claim 1 wherein said chip carrier and said circuit board are
formed of the same material.
3. (Cancelled)
4. The package as defined in claim 1 wherein said first set of solder
connections is formed of a higher melting point solder than said second set of
solder connections.
5. The package as defined in claim 1 further characterized by [the pattern of
said] first bonding pads being more closely spaced to each other [finer] than [the
pattern of the] said second bonding pads.
6. The package as defined in claim 1 wherein the thermal coefficient of
expansions of the material of the chip carrier and the material of the circuit board
do not differ by more than about 20%.
7. A method of mounting integrated circuit chips onto a circuit board
comprising the steps of:
providing an integrated circuit chip having a surface array of input/output
pads on one side thereof which array forms a footprint;
providing a chip carrier formed of an organic glass filled epoxy dielectric
material having first and second opposite surfaces;
said chip carrier having a coefficient of thermal expansion of at least
17×10-6 ppm/c°;
forming a first set of bonding pads on said first surface of the chip carrier
arranged in an array corresponding with the chip footprint;
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