Appeal 2006-1454
Application 09/004,524
Patent 5,483,421
providing a pattern of conductors on said chip carrier connected to
accommodate said input/output pads;
forming a first set of solder connections between the input/output pads on
the chip and said first set of bonding pads on the chip carrier;
an encapsulation material encapsulating said first set of solder connections;
forming a second set of bonding pads on the second surface of the chip
carrier arranged in an array;
forming electrically conducting vias through the chip carrier to connect said
first set of bonding pads to the second set of bonding pads;
providing a circuit board formed of an organic material having a coefficient
of thermal expansion similar to the chip carrier;
forming a set of electrical connection sites on said circuit board arranged in a
pattern corresponding to the pattern of the array of the second bonding pads on
said chip carrier;
forming a second set of solder connections between the pads of said second
set of bonding pads on the chip carrier and the connection sites on the circuit
board; and
forming wiring on said circuit board connected to said second set of bonding
pads.
8. The method of claim 7 wherein said chip carrier and said circuit board are
formed of the same material.
9. (Cancelled)
10. The method as defined in claim 7 wherein said first set of solder
connections is formed of a higher melting point solder than said second set of
solder connections.
11. The method as defined in claim 7 further characterized by first bonding
pads being more closely spaced to each other than said second bonding pads.
12. The method as defined in claim 7 wherein the thermal coefficient of
expansions of the material of the chip carrier and the material of the circuit board
do not differ by more than about 20%.
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