Appeal 2006-1454
Application 09/004,524
Patent 5,483,421
Appendix 4
CLAIMS OF U.S. PATENT 5,483,421, AS RENUMBERED AT ALLOWANCE
1. A package mounting integrated circuit chips onto a circuit board
comprising:
an integrated circuit chip having a surface array of input/output pads on one
side thereof which array forms a footprint;
a chip carrier formed of an organic glass filled epoxy dielectric material
having first and second opposite surfaces;
said chip carrier having a coefficient of thermal expansion of at least
17×10-6 ppm/c°;
a first set of bonding pads formed on said first surface of the chip carrier and
arranged in an array corresponding with the chip footprint;
a pattern of conductors on said chip carrier connected to accommodate said
input/output pads;
a first set of solder connections interconnecting the input/output pads on the
chip to said first set of bonding pads on the chip carrier;
an encapsulation material encapsulating said first set of solder connections;
a second set of bonding pads formed on the second surface of the chip
carrier arranged in an array;
electrically conducting vias extend through the chip carrier connecting said
first set of bonding pads to the second set of bonding pads;
a circuit board formed of an organic material having a coefficient of thermal
expansion similar to the chip carrier;
a set of electrical connection sites formed on said circuit board and arranged
in a pattern corresponding to the pattern of the array of the second bonding pads on
said chip carrier;
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