Appeal 2006-3123
Application 10/368,789
ASIC design for violations of the via sufficiency rules (col. 11, ll. 19-23)
(emphasis added). Thus, the Examiner concludes that Yu discloses the
recited limitations (Answer 7).
We will sustain the Examiner’s rejection of claim 2 for essentially the
same reasons argued by the Examiner in the Answer. We agree with the
Examiner that Yu’s power checker program processes one or more selected
layers of the ASIC design for violations of via sufficiency rules. In
particular, we note that Yu broadly discloses substrate 66 and die 62 as
layers of an electronic design (Fig. 2, col. 3, l. 22). Thus, we find that the
layers of Yu’s electronic design are processed as necessary to detect
violations of via sufficiency rules (see “Via Checker” discussion, col. 11, ll.
46-67).
Claim 3
Appellants argue that Yu fails to disclose a via sufficiency rule
defining a via per pad count for one layer of the electronic design (Br. 11).
The Examiner disagrees. The Examiner notes that Rule 6.1 generates
an error if the number of vias is less than the minimum recommended for a
standard cell rail (Fig. 10). The Examiner points out that these power and/or
ground metal lines (i.e., “rails”) are intersected by vias to provide power to a
standard cell. The Examiner further notes that Yu’s “via checker” program
flags an error when the number of via at the intersection is insufficient, as
determined by Yu’s via sufficiency rules (col. 5, ll. 60-63). The Examiner
concludes that Yu’s via checker program must count the number of vias at
intersections in each layer in order to check for the proper number of vias
(Answer 11).
7
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