Appeal 2006-3123
Application 10/368,789
We agree with Appellants that Yu fails to disclose a via sufficiency
rule that explicitly or inherently defines a via count per pad for one layer of
the electronic design. Therefore, we will reverse the Examiner’s rejection of
dependent claim 19 for the same reasons discussed supra with respect to
dependent claim 3.
Claim 20
Appellants argue that Yu fails to disclose or suggest responding to
designer input to scope the instructions for determining instances of power
and ground vias (Br. 14).
The Examiner disagrees (Answer 11). The Examiner notes that
Yu discloses a via checker that verifies a minimum number of vias to be
used in the special via rule for producing vias for a standard cell
power/ground routing to the mesh within the ASIC design (col. 11, ll. 53-
65). The Examiner notes that Yu discloses if the user moves the cursor over
an error marker, a text description of the error will pop up (e.g., indicating
insufficient via array size, VDD/VSS, short unconnected VDD/VSS) (col. 5,
ll. 62-65) (Answer 11). The Examiner asserts that the process of moving the
cursor by the user or designer corresponds to “responding to designer inputs
to scope the instructions for determining instances of power and ground
vias,” as claimed (id.).
We note that Yu discloses responding to designer input to scope the
instructions for determining instances of power elements:
The method further includes providing a user with
a choice of which power elements in the design to
check, and executing the power checker modules
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