Appeal 2006-3363
Application 10/873,363
2. After the underlying semiconductor device is fabricated, a
dielectric system, item 32, is formed over the semiconductor
device. Col. 3, ll. 60-62.
3. This dielectric system 32 provides a smooth surface to deposit the
GMR material and has properties to provide a barrier for moisture
and oxidation. Col. 4, ll. 5-11, 20-24.
4. A layer of GMR material is formed on top of dielectric system 32
and formed into a magnetic memory cell. Col. 4, ll. 36- 44.
5. A dielectric cap is formed over the magnetic memory cell. Col. 4,
l. 67 – col. 5, l. 4.
6. Tehrani states “[c]ap 45 is provided to seal GMR memory element
41 and provide a barrier to moisture, oxidation, and corrosive
agents for subsequent operations and permanent use. Dielectric
cap 45 includes at least one barrier layer which, in conjunction
with the barrier properties of dielectric system 32 beneath GMR
memory elements 41, seals elements 41 in a substantially complete
barrier.” Col. 5, ll. 1-8.
7. From this disclosure, we find that one skilled in the art would
recognize that one layer of cap 45 covers and provides protection
of the top and sides of the GMR element while the dielectric
system 32 provides protection of the bottom of the GMR element.
8. The dielectric cap consists of several layers of different materials,
one of which masks the barrier layer for etching. Col. 5, ll. 8-21.
9. Tehrani teaches that there are two methods of etching the vias 47
(which are through both layers 45 and 32) and vias 50 (which are
through parts of layer 45). See figure 7.
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