Appeal 2007-2460
Application 10/709,179
pattern 11, and a first dielectric layer 12 covering top and side
surfaces of the first interconnect pattern 11. A second
interconnect pattern 14 is formed on the first dielectric layer 12
and is connected to the first interconnect pattern 11 via through-
holes 13 that are formed in the first dielectric layer 12 to
penetrate the same. A semiconductor chip 15 is mounted on the
first dielectric layer 12, and bonding wires 17 connect chip
electrodes 16 formed on the semiconductor chip 15 with the
second interconnect pattern 14. A encapsulating resin 18
encapsulates the semiconductor chip 15 and the bonding wires
17 on the first dielectric layer 12, and metallic bumps 19
constituting the external electrodes are formed on the bottom
surface of the first interconnect pattern 11. An adhesive
dielectric sheet 20 that constitutes a second dielectric layer
covers the bottom surface of the first interconnect pattern 11
and exposes the bottom surface of the metallic bumps 19.
(Id. at ¶ 28).
8) Ono states that its Figure 3 is an example of a first interconnect
pattern from a top view. (Id. at ¶ 29).
9) Ono states that the interconnect patterns may be formed from Ni, Cu
and Au. (Id. at ¶ 56).
2. Akram, U.S. Pat. 6,861,763
10) Akram describes a method for forming packaged substrates. (Akram,
Abstract).
11) Akram describes forming an array of bond pads at an active surface of
a die, attaching conductive structures, such as conductive bumps to the
7
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