Appeal 2007-2494
Application 10/161,134
The Examiner has rejected claims 12-17 and 58-60 under 35 U.S.C.
§ 103(a) (Answer2 at 3, 7, 8 and 10). The Examiner relies on the following
prior art3 of record:
Kim US 5,986,318 Nov. 16, 1999
Su US 6,133,096 Oct. 17, 2000
Ilg US 6,492,688 B1 Dec. 10, 2002
Mason JP 10-163,0834 Jun. 19, 1998
Wolf, SILICON PROCESSING FOR THE VLSI ERA: Volume 2:
Process Integration, Lattice Press, Sunset Beach, California (1990),
48-49 and 435.
Kim, Su and Ilg qualify as prior art under 35 U.S.C. § 102(e). Mason and
Wolf qualify as prior art under 35 U.S.C. § 102(b). According to the
Examiner, claims 12-14 and 58 would have been obvious over the combined
teachings of Mason and Su; claims 15 and 17 would have been obvious over
the combined teachings of Mason, Su and Wolf; claims 59 and 60 would
have been obvious over the combined teachings of Mason, Su and Ilg; and,
claim 16 would have been obvious over the combined teachings of Mason,
Su, Wolf and Kim (Answer at 3, 7, 8 and 10).
II. Findings of Fact ("FF")
The following findings of fact are supported by a preponderance of
the record.
2 Examiner's Answer mailed 18 August 2006 ("Answer").
3 No references to et al. are made in this opinion.
4 This decision relies on and cites to the English translation of Mason
obtained by the USPTO from FLS, Inc. in June 2006.
3
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