Appeal No. 96-0576
Application 07/846,231
The invention relates to a system and method for sending
simultaneous READ/WRITE requests to at least two subsystems and
subsequently canceling the request not needed. Appellants
disclose on pages 10 through 12 of the specification with
reference to Figures 1, 3B and 5, that when code 310 of an
instruction is decoded by IPU 105 and when operation code 310
indicates that an access to one of the resources, IOU 130 or MCU
120, is required, each of the resources, IOU 130 or MCU 120, is
immediately activated by sending to both IOU 130 and MCU 120 a
READ/WRITE request 520. When the remainder of the instruction is
decoded by MCU 120 and it is determined which of the resources,
either IOU 130 or MCU 120, is needed to be accessed, the MCU 120
issues a cancellation signal. If it is determined that the IOU
130 is performing the READ/WRITE operation, the MCU 120 issues a
cancellation signal to itself to cancel its own READ/WRITE
request. If it is determined that the MCU 120 is performing the
READ/WRITE operation, the MCU 120 issues a cancellation signal to
IOU 130 to cancel the IOU 130 READ/WRITE request.
The independent claim 1 is reproduced as follows:
1. A method for reducing the critical path in a processor
based system during READ/WRITE operations, the system having
a memory control unit (MCU), an Input/OutPut control unit
(IOU) and an instruction set comprising the steps of:
2
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