Appeal No. 96-0576
Application 07/846,231
access to the resources is required as recited in Appellants’
claims.
In addition, we note that Stinson does teach in column 4,
lines 24-67, that the status of the microprocessor 1 is
determined by the Early READ/WRITE logic circuit 12 which
determines if the microprocessor 1 is reading or writing to
memory. If the Early READ/WRITE logic circuit 12 determines that
the microprocessor is reading or writing to memory, the Early
READ/WRITE logic circuit 12 sends a memory write (MWT) signal 14
or a memory read (MRD) signal 15 to the memory bus interface 20.
When a memory bank receives an appropriate address from the
microprocessor 1 and a MRD or MWT signal, the memory bank
responds back over the memory bus interface 20 with a RAM
acknowledgment signal to signal to the microprocessor 1 that the
memory bank will be ready to complete the READ or WRITE cycle.
Stinson teaches that this ensures maximum throughput of the
unified bus interface during the READ or WRITE operation.
However, Stinson fails to teach decoding the remainder of
the instruction to determine the address(es) to be accessed,
decoding the address(es) to be accessed, decoding performed by at
least one of the resources to determine which of said at least
8
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 Next
Last modified: November 3, 2007