Appeal No. 96-0576
Application 07/846,231
(c) means for sending a request to at least two of the
resources to enter an access state if it is determined
by said means for determining that access to the
resources is required;
(d) means for decoding the remainder of the instruction
to determine the address(es) to be accessed;
(e) means for decoding the address(es) to be accessed,
decoding performed by at least one of the resources to
determine which of said at least two of the resources
will be accessed; and
(f) means for canceling the remainder of the requests
based on the results of the decoded address(es).
Upon a careful review of Stinson, we fail to find that the
reference teaches the above limitations as recited in Appellants’
claims.
Stinson does teach in column 3, lines 17-22, that the
microprocessor 1 shown in Figure 1 has three status lines 13.
Furthermore, Stinson teaches in column 4, lines 24- 27, that the
microprocessor outputs a status on the status lines 13 to
indicate when the microprocessor 1 is reading or writing to
memory. However, Stinson is silent as how this status is
determined. Stinson fails to teach that the Stinson’s
microprocessor decodes a first part of an instruction from the
instruction set, determines if said instruction requires an
access operation and sends a request to at least two of the
resources to enter an access state if it is determined that
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