Ex parte YOSHIYUKI MIYAYAMA et al. - Page 5




          Appeal No. 96-0576                                                          
          Application 07/846,231                                                      


               Appellants argue on pages 9 through 13 of the brief that               
          Stinson fails to teach or suggest decoding a first part of an               
          instruction to determine if a READ or a WRITE operation is                  
          required and if such operation is required sending to the system            


          resources a request to place these resources in a READ/WRITE                
          state.  Appellants further argue that Stinson fails to teach or             
          suggest that once the remainder of the instruction is decoded,              
          and it is determined which resource is to be accessed, the                  
          requests to the other resources are canceled.  Appellants further           
          emphasize on pages 3 through 5 of the reply brief that Stinson              
          fails to teach the above claimed limitations as recited in                  
          Appellants’ claims.                                                         
               We note that Appellants’ claim 1 recites in part the                   
          following:                                                                  
               (a) decoding a first part of an instruction from the                   
               instruction set;                                                       
               (b) determining if said instruction requires at least                  
               one of a READ and a WRITE operation;                                   
               (c) sending a request to both the MCU and the IOU to                   
               enter the READ/WRITE state if it is determined in step                 
               b that a READ and/or a WRITE is required;                              
               (d) decoding the remainder of the instruction to                       
               determine the address(es) to be accessed by the READ                   
               and/or WRITE operation;                                                

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