Appeal No. 1997-0708
Application 08/196,618
This is a decision on appeal under 35 U.S.C. § 134 from
the final rejection of claims 1, 2, 4-7, 9, and 10. Claims 3
and 8 stand objected to as being dependent upon a rejected
base claim.
We reverse.
BACKGROUND
The disclosed invention is directed to a method and
apparatus for checking cache coherency. "Snoop" refers to
monitoring bus traffic to maintain cache coherency. When a
main memory bus transaction occurs to an address which is
replicated in the cache, a snoop hit is detected and
appropriate actions are taken. The invention provides a
double cache snoop mechanism, i.e., a cache mechanism in which
each snoop has the possibility of being sent to the cache
twice, first a read-only request to determine if there is a
hit and, if so, a read-write request to modify the cache.
This reduces the average number of cycles that a processor is
stalled or locked during a coherency check.
Claim 1 is reproduced below.
1. An apparatus for checking cache coherency in a
computer architecture having a system memory
interconnected by a system bus to at least two modules,
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