Appeal No. 1997-0708
Application 08/196,618
not a "read-write request" (emphasis added), but is only a
write. As to point (2), the Examiner states that the
avoidance of at least one write operation is not stated in the
claims (EA4-5). This is true. However, since all cache
misses will avoid a write operation and since cache misses
will be a frequent occurrence (the specification indicates
this will happen 90% of the time, page 10, lines 1-6), the
advantage of the double snoop cannot be ignored. As to point
(3), the Examiner finds that one piece of hardware cache
performs an access twice in sequence (EA5). Our response to
point (1) also applies here. The Examiner has not shown that
Thacker teaches one piece of hardware cache that is accessed
twice in sequence as claimed. As to point (4), in response to
Appellants' argument that it would not have been obvious to
perform a double snoop in Thacker, the Examiner states that
the test for obviousness is not whether features may be bodily
incorporated but simply what the reference makes obvious to
one of ordinary skill in the pertinent art (EA5-6). This does
not respond to Appellants' argument.
The Examiner further states (FR2):
As to claims 1 and 6, Thacker et al. did not show
each module including a clock for interrupting access to
- 8 -
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 Next
Last modified: November 3, 2007