Appeal No. 1997-0708
Application 08/196,618
The Examiner finds that Thacker discloses "a bus
interface [264 and 274] associated with each module [120 and
122] for receiving requests to check [Comp 262 or 272]" (FR2).
Buffers 264 and 274 may be a bus interface in the sense that
they interface with the data bus, but they are not a bus
interface for receiving requests to check cache coherency.
Nevertheless, our own reading of Thacker shows a shared bus
interface 280 which receives a request to check cache
coherency and transmits a cache check request on line 278 to
the logic 276 in cache 122 (col. 8, approx. lines 30-40).
The Examiner further finds (FR2) that the claimed
"first[] read-only request to said cache" is providing address
bits AB to comparator 262 and that the claimed "second
read-write request that is forwarded to said cache if and only
if said first read-only request indicates that said cache
address tag matches an address of said request to check cache
coherency and said request to check cache coherency requires
said cache to be modified as a result of any of invalidation,
copying out, or changing from clean to shared status" reads on
providing address bits A to comparator 272.
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