Appeal No. 1997-0708
Application 08/196,618
This interpretation is in error for several reasons.
First, the "first[] read-only request" and the "second
read-write request" must go to the same cache, whereas the
examiner finds the "first, read-only request" in first level
cache 120 and the "second read-write request" in the second
level cache 122.
Second, cache coherency checking is not performed in the
first level cache 120. Data may be written to the first level
cache 120 and, if it is, it is also written to the second
level cache 122 (col. 7, lines 5-9). However, the first level
cache 120 does not receive a request for checking cache
coherency. Only the second level cache receives a request for
checking cache coherency (from bus interface 280 via line 278;
col. 8, lines 30-40, which is under the heading "CACHE
COHERENCY" in col. 7). "The goal of the invention is to avoid
accessing the first level cache for cache coherence checking,
unless the updated location is actually stored in the first
cache, because unnecessary coherence checking accesses to the
first cache interfere with access by the processor and reduce
the performance of the system." (Col. 2, lines 42-47). Thus,
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