Appeal No. 1997-0708
Application 08/196,618
at least one of said modules having an associated cache
memory for storing cache contents therein, comprising:
a cache address tag associated with each cache for
indicating said cache contents status;
a bus interface associated with each module for
receiving requests to check cache coherency, and for
forwarding said requests to said cache; said bus
interface forwarding a first, read-only request to said
cache, followed by a second read-write request that is
forwarded to said cache if and only if said first
read-only request indicates that said cache address tag
matches an address of said request to check cache
coherency and said request to check cache coherency
requires said cache to be modified as a result of any of
invalidation, copying out, or changing from clean to
shared status; and
each module including a lock for interrupting access
to said cache only during a read-only request and a
subsequent read-write request pursuant to a cache
coherency check.
The Examiner relies on the following prior art:
Thacker 5,136,700 August 4, 1992
Claims 1, 2, 4-7, 9, and 10 stand rejected under
35 U.S.C. § 103 as being unpatentable over Thacker.
We refer to the Final Rejection (Paper No. 7) (pages
referred to as "FR__") and the Examiner's Answer (Paper
No. 14) (pages referred to as "EA__") for a statement of the
Examiner's position and to the Corrected Appeal Brief filed
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