Appeal No. 97-2473 Page 3
Application No. 08/264,582
BACKGROUND
The invention at issue in this appeal relates to
interconnecting the components of a multi-processor system.
It interconnects the system’s plural processors and plural
memories by a crossbar switch. The switch can be reconfigured
to achieve
different combinations of distributed and shared memory
arrangements. The switch, processors, and memories are
integrated on a single chip to facilitate communications among
these components.
Claim 68, which is representative for our purposes,
follows:
68. A multi-processing system comprising:
a plurality of n processors, each of said
processors operable from an instruction stream
provided from a memory source for controlling a
process, said process relying on the movement of
data to and from one or more addressable memories,
each processor having a first data port and a second
data port;
a plurality of m memory sources, each memory
source having a unique addressable space;
a switch matrix having first links connected to
said memories and second links connected to said
first and second data ports of said processors, said
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