Appeal No. 97-2473 Page 11
Application No. 08/264,582
(Examiner’s Answer at 6, Final Rejection at 2.) Indeed,
Figures 2 and 3 of Barnes depict only a single port in each
processor for coupling it to the connection network. The
reference, furthermore, lacks any teaching of or suggestion to
restrict access of the single port to only a subset of the
memory modules.
Chang teaches a computer having a plurality of
processors. One processor is a master processor 26; the
others are slave processors 20, 22, and 24. Each processor is
connected through an interconnection switch 42 to a shared
multiaccess memory (MAM) with multiple memory modules 44, 46,
48, and 50. Col. 2, ll. 12-21.
The examiner does not show or even allege that Chang
discloses two data ports. In fact, Figures 2 and 8 of Chang
depict only a single data line between each of the slave
processors and the interconnection switch. Figure 9 similarly
depicts only a single MAM interface 130, with a single data
port, for each processor. Chang lacks any teaching of or
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