Appeal No. 97-2473 Page 9
Application No. 08/264,582
al.[,s] system.” (Id. at 4-5.) The examiner adds, “[s]ince
the steps in the method claims are performed by the apparatus
of the apparatus claims, the method claims are rejected based
on the rejections of the apparatus claims.” (Id. at 5.) “As
to claim the master processor of claim 82,” asserts the
examiner, “Barnes et al. [E]xactly taught master control for
instruction scheduling and synchronization control ....”
(Id.)
In response, the appellants submit that neither Barnes
nor Chang “contain any indication that each of the processors
have the two data ports” recited in independent claims 68, 74,
and 82. (Appeal Br. at 7.) They also submit that Chang
“includes no teaching” that the reference’s interconnection
switch allows connection of the two data ports of its
processors to differing sets of memories. (Id. at 9.) In
addition, the appellants argue that neither the combination of
Barnes and Ewert nor Ewert alone teaches “or makes obvious”
the subject matter of the first data port of each processor
having access to all memories while the second data port of
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