Appeal No. 97-2473 Page 12
Application No. 08/264,582
suggestion to connect the data port of a processor to only a
subset of the MAM modules. To the contrary, the reference
discloses that the interconnection switch can be configured so
that any processor is connected to any MAM module. Id. at
col. 3, ll. 36-40.
Ewert discloses a parallel digital processor including a
plurality of parallel processing modules (PPMs) coupled to a
common, main memory. Col. 17, ll. 9-11. Each PPM includes
three ports, col. 4, l. 3, including two data ports. Col. 2,
ll. 52-55. The first and second data ports are associated
with A register 12 and B register 13, respectively, in the
PPM. Col. 4, ll. 3-5.
The memory is organized in rows and columns. A single,
separate memory column is dedicated to each port. Id. at col.
2, ll. 59-60. For example, MA1 memory column 22 is coupled to
A register 12 of the PPM via A-bus 32. MB1 memory column 23
is coupled to B register 13 via B-bus 33. In contrast to the
claimed invention, which permits the first port access to any
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