Appeal No. 97-2473 Page 4
Application No. 08/264,582
switch matrix selectively connecting said first and
second links whereby said first data port of each of
said n processors may access any of said m memory
sources and said second data port of each of said n
processors may access only a predetermined
corresponding subset of said m memory sources.
(Appeal Br. at 18.)
The references relied on by the patent examiner in
rejecting the claim follow:
Barnes et al. (Barnes) 4,365,292 Dec. 21,
1982
Chang 5,056,000 Oct. 8,
1991
(effective filing date of June 21,
1988)
Ewert 5,247,689 Sept. 21,
1993
(effective filing date of Feb. 25,
1985).
Claims 68, 69, 72-77, and 80-83 stand rejected under 35
U.S.C. § 103 as obvious over Barnes in view of Chang or Ewert.
(Examiner’s Answer at 4.) Rather than repeat the arguments2
of the appellants or examiner in toto, we refer to the appeal
2Claims 70, 71, 78, and 79 stand objected to as being
dependent on rejected base claims. (Examiner’s Answer at 2.)
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