Appeal No. 97-2473 Page 10
Application No. 08/264,582
each processor has access to only a subset of the memories.
(Reply Br. at 4.)
Regarding independent claims 68, 74, and 82; we find
Barnes, Chang, and Ewert fail to teach or to have suggested
the first and second data ports as claimed. The claims recite
in pertinent part that each of a plurality of processors has a
first and a second data port. The claims further recite that
a switch matrix is connected to the ports, by which the first
port may access “any of said m memory sources,” (Appeal Br. at
18, 20, 22), while the second port may access “only a
predetermined corresponding subset of said m memory sources.”
(Id.) Comparison of the claim language to Barnes, Chang, and
Ewert, evidences that the references neither teach nor would
have suggested the claimed first and second data ports.
Barnes discloses a connection network 15 for
interconnecting an array of data processors 29 with an array
of memory modules 13. Col. 1, ll. 13-15. The examiner admits
that the reference does not disclose two data ports.
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