Appeal No. 1998-1365 Page 12
Application No. 08/663,969
signal are substantially aligned by counting a number of
cycles of said clock signal occurring in a predetermined
period of time.” Therefore, we affirm the rejection of claims
27, 28, 31, 35-37, 40, and 44 as obvious over Marshall in view
of Vanderspool.
Further regarding claims 32, 33, 41, and 42, the
appellants argue, “neither Marshall nor Vanderspool teaches
that the number of cycles counted within the determining
circuitry or step is equal to the multiple when the clock
signal generator is operating correctly.” (Appeal Br. at 8.)
Representative claim 41 specifies in pertinent part the
following limitations: “said clock signal ... is equal to a
multiple of said reference clock signal” and “said number of
cycles is equal to said multiple when said clock signal
generator is operating correctly.” Giving the claim its
broadest reasonable interpretation, the limitations recite
that the frequency of the clock signal is a multiple of the
frequency of the reference clock signal and that the number of
cycles of the clock signal occurring in a predetermined period
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