Appeal No. 1998-1365 Page 15
Application No. 08/663,969
frequency of the clock signal is a multiple of the frequency
of the reference clock signal.
Vanderspool further teaches that the number of cycles of
the clock signal occurring in a predetermined period of time
is equal to the multiple when the clock signal generator is
operating correctly. As aforementioned regarding the
appellants’ first argument, the reference counts a number of
cycles of the sampled clock occurring during each cycle of the
1PPS signal. Because the frequency of the sampled clock is
50,000 times greater than that of the 1PPS signal, 50,000
cycles would be counted when the apparatus of the Vanderspool
is operating properly.
In view of the aforementioned teachings, we are persuaded
that either Marshall or Vanderspool, in combination with the
prior art as a whole, teaches the claimed limitation of “said
clock signal ... is equal to a multiple of said reference
clock signal” and “said number of cycles is equal to said
multiple when said clock signal generator is operating
correctly.” Therefore, we affirm the rejection of claims 32,
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