Ex parte HO - Page 11




                 Appeal No. 1998-1069                                                                                                                   
                 Application No. 08/259,575                                                                                                             


                 an n-type first well 8 by implanting ions at 160 keV, forming                                                                          
                 a                                                                                                                                      
                 p-type second well 5 by implanting ions at 160 keV, forming an                                                                         
                 oxide layer 3 & 7a, and forming first and second gate                                                                                  
                 structures 17.  The Examiner then states  that Schwabe does             15                                                             
                 not disclose forming first and second gate structures from                                                                             
                 polysilicon, performing a first LDD implant concurrently into                                                                          
                 the first and second wells, forming sidewalls, and performing                                                                          
                 separate implants at 40-180 keV at a dose in the range of 1015                                                                         
                         16                2                                                                                                            
                 - 10  atoms/cm .                                                                                                                       
                          The Examiner then adds  Bergonzoni's disclosure of16                                                                                    
                 forming first and second gate structures 6 from polysilicon,                                                                           
                 performing a first LDD implant concurrently into the regions                                                                           
                 where the first and second CMOS transistors are to be formed,                                                                          
                 and forming sidewalls 8.  The Examiner argues that although                                                                            
                 Bergonzoni does not disclose forming an NMOS device within a                                                                           
                 p-type well, forming the NMOS device within a p-type well                                                                              




                          15Final rejection, page 6                                                                                                     
                          16Final rejection, page 7                                                                                                     
                                                                          11                                                                            





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