Appeal No. 1999-1631
Application 08/733,586
The invention relates to the layout design of static
random access memory (SRAM) cells. Figure 1A is the circuit
diagram of
a prior art SRAM having: a first inverter 12, which includes a
p-type pull-up transistor 20 and an n-type pull-down
transistor 24; a second inverter 14, which includes a p-type
pull-up transistor 22 and an n-type pull-down transistor 26;
and two pass transistors, 16 and 18. In the prior art layout
shown in Figure 1B, gates 90 and 94 of transistors 20 and 24
in inverter 12 are offset in the vertical (i.e., y) direction
but not in the horizontal direction. The same relationship
applies to gates 92 and 96 of transistors 22 and 26 in
inverter 14.
In the prior art layout of Figure 1C, gate 90 of
transistor 20 is offset horizontally to the left relative to
gate 94 of transistor 24, while gate 92 of transistor 22 is
offset horizontally to the right relative to gate 96 of
transistor 26.
In appellant's first embodiment (Figure 2), both
horizontal offsets are in the same direction, i.e., gate 140
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