Appeal No. 1999-1631
Application 08/733,586
a pair of pass transistors connected between
said pair of bitlines and said pair of cross-coupled
inverters.
5. A static random access memory (SRAM) device
comprising a plurality of cells, each of said cells
comprising:
a first inverter comprising a first p-channel
transistor centered at a first x-co-ordinate [sic; x
co-ordinate] and a first n-channel transistor
centered at a second x co-ordinate;
a second inverter cross-coupled with said first
inverter and comprising a second p-channel
transistor centered at a third x co-ordinate and a
second n-channel transistor centered at a fourth x-
co-ordinate [sic], wherein a mean of said first and
third x co-ordinates is unequal to a mean of said
second and fourth x co-ordinates, said first and
second n-channel transistors being roughly aligned
which defines the x direction; and
a pair of pass transistors connected to said
first and second inverters.
10. A static random access memory (SRAM) cell
comprising:
a first inverter comprising a first p-channel
transistor and a first n-channel transistor, said
first p-channel transistor being offset in both the
horizontal and vertical directions from said first
n-channel transistor;
a second inverter cross-coupled with said first
inverter and comprising a second p-channel
transistor and a second n-channel transistor, said
second p-channel transistor being offset from the
second n-channel transistor in the same horizontal
and vertical directions as the first p-channel and
first n-channel transistors, and with said first and
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