Appeal No. 1999-1631
Application 08/733,586
of transistor 106 (in inverter 102) is offset horizontally to
the right relative to gate 142 of transistor 110 (in inverter
102), and gate 144 of transistor 108 (in inverter 104) is
offset horizontally to the right relative to gate 146 of
transistor 112 (in inverter 104).
In appellant’s second embodiment (Figure 3), the
horizontal offsets are in the same direction but in different
amounts, i.e., gate 240 of transistor 206 (inverter 202) is
offset horizontally to the right by a first amount relative to
gate 242 of transistor 210 (inverter 202), and gate 244 of
transistor 208 (inverter 204) is offset horizontally to the
right by a second, smaller amount relative to gate 246 of
transistor 212 (inverter 204).
The amount of horizontal offset in appellant's
embodiments can be described as the difference between the p-
channel mean (xnm) and the n-channel mean (xnm), where the x
co-ordinates of the center points of the gates of the first
and second p-channel transistors are xp1 and xp2, the x co-
ordinates of the center points of the gates of the first and
second n-channel transistors are xn1 and xn2, the p-channel
mean (xpm) equals (xp1+xp2)/2, and the n-channel mean (xnm)
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