Appeal No. 1999-1631
Application 08/733,586
equals (xn1+xn2)/2 (Specification at 6, ll. 19-26). The
difference between the two means can be in the range from the
minimum feature size of a given technology (e.g., 0.5 microns)
up to one-half the width of the cell (id. at 6, l. 26 to p. 7,
l. 1).
B. The claims
The independent claims, i.e., claims 1, 5, and 10, read
as follows:2
1. A static random access memory (SRAM) cell
comprising:
a pair of cross-coupled inverters, a first of
said inverters comprising a first p-channel pull-up
transistor and a first n-channel pull-down
transistor, a second of said inverters comprising a
second p-channel pull-up transistor and a second n-
channel pull-down transistor, wherein a gate of said
first p-channel pull-up transistor is offset from a
gate of the first n-channel pull-down transistor in
the same horizontal direction as a gate of the
second p-channel pull-up transistor is offset from a
gate of the second n-channel pull-down transistor,
and said n-channel pull-down transistors are
laterally aligned;
a pair of bitlines extending in a vertical
direction; and
2In Claim 10 as reproduced in the Appendix to the Brief,
line 2 incorrectly includes the term "gate" after "transistor"
(first occurrence). The examiner also correctly notes (Answer
at 3) that dependent claim 6 is incorrectly reproduced in that
Appendix -- the value "0.25" should read "0.5."
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