Appeal No. 1999-0133
Application No. 08/459,570 Page 6
examiner adds (answer, page 6) that appellants' invention allows
routing of more product terms to each output line by using larger
demultiplexers and correspondingly larger logic gates than
Agrawal. The examiner asserts (id.) that:
Demultiplexers and logic gates are notoriously well-
known in the art of digital logic design and can be
designed to provide varying numbers of outputs and
inputs, respectively, by way of well-known design
techniques (i.e., basic CMOS design).
Thus, it would have been obvious to one of
ordinary skill in the art at the time of applicant’s
invention to have increased the numbers of the product
terms routed to each output line as a matter of design
choice in order to increase and/or optimize the
programmability of the logic allocator of Agrawal.
In the examiner's view, (id.) the number of routable product
terms available to each output is a result effective variable
which depends upon the sizing of the demultiplexer and logic
circuits, and appellants appear "merely to be optimizing the
device to include a particular, optimal value of product[-]terms
available to each output." With regard to independent claims 13
and 28, the examiner's position (answer, page 7) is that Agrawal
does not disclose each output line having programmable access to
at least five input lines. The examiner asserts (id.) that
“[s]imilarly as above, it would have been obvious to one of
ordinary skill in the art at the time of applicant’s invention to
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