Appeal No. 1999-0133
Application No. 08/459,570 Page 8
[An] ordinarily skilled artisan would be motivated to
improve programmability (or functionality) at the
expense of some speed performance if the improvement in
programmability is critical or important to the
application at hand while the corresponding decrease in
speed is not as critical or important.
We find that Agrawal discloses (col. 5, lines 19 and 20) that
"[f]or a high density PAL-like device[,] achieving higher speed
is extremely critical." Agrawal further discloses (col. 5, lines
29-32) that the programmable logic device "gives an optimum
balance between functionality, silicon die size, and
performance."
From the disclosure of Agrawal that speed is critical and
that an optimum balance should be provided between functionality,
silicon die size and performance, we find no suggestion to
increase functionality (programmability or routability) at the
expense of performance (speed) by modification of the logic
allocator to provide each output line of the logic allocator with
programmable access to the claimed numbers of product-terms and
input lines. As noted by appellants (reply brief, page 5):
In the instant invention, Applicants did not
optimize programmability at the expense of speed as
hypothesized by the Examiner. Rather, “[a]
programmable optimized-distribution logic allocator ...
enhances the speed, silicon utilization, logic
efficiency, logic utilization, and scalability of very
high-density complex PLDs that use[s] the new logic
allocator.”
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