Appeal No. 1999-0133
Application No. 08/459,570 Page 7
have increased the numbers of its input lines routed to each of
the output lines as a matter of design choice to optimize
programmability.”
Upon careful review of the entire record, we find, for the
reasons which follow, that the examiner has failed to establish a
prima facie case of obviousness of independent claims 1, 13, and
28; and agree with the position set forth by appellants in the
brief and reply brief.
Appellants assert (brief, page 9) that the examiner's
proposed modification of the programmability of the logic
allocator is a conclusionary, simplistic comment that contradicts
the disclosure of Agrawal of providing optimum balance between
functionality, silicon die size and performance, and (brief, page
10) Agrawal's teaching that speed performance of the device is
important.
The examiner acknowledges (answer, page 10) that the state
of the art optimizes according to the variables that appellants
have stated, but asserts that "improvements in any one of
functionality, silicon die size and performance (i.e. speed) all
involve corresponding tradeoffs with regard to the other
factors." In the examiner's view (answer, page 11):
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