Appeal No. 1999-0133
Application No. 08/459,570 Page 9
In addition, we find the examiner's reliance on In re
Boesch, 617 F.2d 272, 276, 205 USPQ 215, 219 (CCPA 1980) to be
misplaced, as the examiner has not pointed to any disclosure in
Agrawal, or within the knowledge of an artisan that would teach
or suggest the kind of experimentation necessary to achieve the
claimed product terms or input lines for each output line of the
logic allocator. As noted by appellants (brief, pages 13 and 14)
the benefits of providing the claimed programmability (as
disclosed on pages 13 and 14 of appellants' specification) is
that:
First, the need for “wrap-around” at the
boundaries of the programmable logic array for better
product-term allocation has been obviated. Second, the
need for an output switch matrix between the logic
macrocells and the I/O cells also has been obviated . .
. The programmable optimized-distribution logic
allocator achieves the flexibility of optimal
routability of logic product-term clusters to I/O pins
which allows retaining a prior pin-out while changing a
logic design. In addition, the twenty logic product
terms can be routed to a particular logic macrocell
without any additional speed penalty. This number of
product terms is typically sufficient to allow complete
shuffling of the logic mapped on the PLD with the
ability to retain prior pin-outs and removes any
dependencies of product-term clusters between adjacent
macrocells.
In addition, the fact that demultiplexers and logic gates
are well known in the art of digital logic design does not, by
itself, provide a teaching or suggestion of the specific number
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