Appeal No. 2002-0374 Page 7
Application No. 08/599,227
redundant rows or columns are utilized as defective row or column
replacements. Appellants argue that claim 1 recites the provision
of a plurality of cache lines and "at least one redundant unmapped
cache line in said cache . . . ."
Appellants note (brief, page 5) that in Supnik, a single bit
within a cache line is used to indicate whether a fault exists
within that cache line. The set reserve bit inhibits the use of a
cache line which includes a defect. It is argued that Supnik fails
to show or suggest the provision of redundant cache lines, and that
nothing within Supnik shows or suggests the provision of unmapped
redundant cache lines as set forth in claim 1. Turning to Lucente
and Rastegar, appellants assert (id.) that each of these systems
disclose the well known technique of providing redundant cache
lines which are mapped to a logical equivalent of a defective line.
Specifically, Lucente discloses that locations from an on-chip
fully associative cache are then mapped into the address space in
place of faulty locations, and (brief, page 6) Rastegar discloses
that "the columns containing bad links are disabled, typically by
blowing fuse links, and the redundant columns are enabled to take
their place. Mapping must be done in order to allow the redundant
memory to substitute for bad regions anywhere on the device."
Appellants urge (brief, page 6) that “[a]pplicant respectfully
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