Appeal No. 2002-0374 Page 11
Application No. 08/599,227
order to replace bad memory cells. Enough spare rows or columns
must be provided to replace all of the rows containing bad bits in
most cases, but it is undesirable to provide too many redundant
rows.”
From the disclosure of Rastegar, we find that Rastegar
discloses replacing defective rows with redundant rows in the
cache, and mapping the replacement rows to the location of the
defective rows. We find no teaching or suggestion in Rastegar of
accessing unmapped cache lines as temporary cache locations without
replacing or overwriting any contents within the main memory array,
as required by claim 1. Thus, we find that the prior art
references to Lucente and Rastegar would have suggested replacing
defective lines in Supnik with redundant cache lines, but do not
teach or suggest accessing redundant unmapped cache lines, and
using the unmapped redundant cache lines a temporary cache without
displacing or overwriting any contents within the main array.
We are not persuaded by the examiner's assertion (answer, page
10) to the effect that Rastegar's teaching of mapping redundant
memory to any location on the device which contains non-functional
data, suggests that when being used as a temporary cache location,
mapping is necessary, and redundant unmapped cache lines are used.
We find the examiner's assertion to be unsupported by any evidence
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