Appeal No. 2002-0374 Page 8
Application No. 08/599,227
urges that nothing within the cited references within the present
record shows or suggests in any way the utilization of a ‘redundant
unmapped cache line’ as a temporary cache location as each of the
references cited by the Examiner which teaches the utilization of
redundant cache lines expressly teaches that those cache lines must
be ‘mapped’ into the cache in order to be utilized.”
From our review of Supnik, we find that data errors may be
caused, inter alia, by hardware faults, such as defective memory
storage cells (col. 7, lines 12 and 13). Densely packed storage
cells of high speed cache memories are susceptible to hardware
defects. In order to use cache memories which include a few
defects, an additional bit 58, 60 called a "defect bit" is
incorporated into each entry in the tag storage portions 42, 44 of
cache 22. If the defect bit is set, then the entry contains a
defect and will no longer be used (col. 7, lines 12-22). Once set,
the defect bit essentially removes the entry from the cache (col.
7, lines 31 and 32). The error detecting program (figure 3) loads
all of the memory locations with zeros and then with ones. If any
bit in the memory locations cannot become a binary zero and a
binary one, then the error bit in that location is set so that the
memory location is disabled (col. 7, lines 43-54). Thus, we find
from our review of Supnik that Supnik disables defective bits by
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