Appeal No. 2002-0374 Page 10
Application No. 08/599,227
Turning to Rastegar, we find that a processor, when accessing
a memory, accesses the desired memory location through the cache.
If the memory location is not in the cache, the memory location is
fetched from the main memory (col. 1, lines 35-39). It is known
that memory devices have non-functioning bits as a result of
processing variations. Rather than discard devices having a small
number of ad bits, redundant memory cells are provided. The
columns containing bad bits are disabled, typically by blowing fuse
links, and the redundant columns take their place. Mapping must be
done to allow the redundant memory to substitute for bad regions
anywhere on the device (col. 2, lines 9-19). In Rastegar,
redundant rows are provided to substitute for array rows containing
non-functional bits (col. 2, lines 40-42). The memory array is
divided approximately in half. The bit lines cross over between
array halves to minimize stray capacitance and cross-coupling
capacitance. The redundant rows can be located in the first half
of the array. The second half of the array provides inverted data.
If a redundant row replaces an array row in the second half of the
array, the data must be inverted prior to writing to or reading it
from the redundant row (col. 2, lines 35-51). Rastegar further
discloses (page 9, lines 25-30) that “[i]t is well known in the art
that redundant memory cells can be provided for memory arrays in
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