Ex Parte GEDNEY et al - Page 64



              Appeal 2006-1454                                                                                         
              Application 09/004,524                                                                                   
              Patent 5,483,421                                                                                         

                                                    Appendix 1                                                         
                                          Drawings of application, as filed                                            
              Brief description of the drawings of Gedney et al., U.S. Patent 5,483,421, of which                      
              the present applicant seek reissue (drawing sheets 1-3 are attached).                                    
              FIGURE 1 is a longitudinal section view, somewhat diagrammatic, showing the                              
              connection of a ceramic chip carrier to a glass filled organic circuit board card                        
              (FR-4) by means of solder ball connections, and depicting the stress pattern                             
              generated at elevated temperature due to thermal mismatch.                                               
              FIGURE 2 is a graph plotted to depict the relative deformation of a circuit board                        
              card and ceramic module under thermal stress showing the average normal strain                           
              in each solder ball connection.                                                                          
              FIGURE 3 is a graph showing the relative shear displacement between a circuit                            
              board and a ceramic module showing strain in the planar direction between the                            
              board and module and the average shear strain in each solder ball.                                       
              FIGURE 4 is an exploded perspective view showing the mounting of chips onto a                            
              carrier and carrier onto a circuit card according to the present invention.                              













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