Ex Parte Racanelli - Page 2



            Appeal No. 2006-2832                                                                            
            Application No. 09/833,953                                                                      

                                                 Invention                                                  
                   Appellant describes his invention as follows:                                            
                   According to the invention, a layer is formed over a transistor gate and a               
            field oxide region.  For example, a polycrystalline silicon layer can be deposited              
            over a PFET gate oxide and a silicon dioxide isolation region on the same chip.                 
            The layer is then doped over the transistor gate without doping the layer over the              
            field oxide.  A photoresist layer can be used as a barrier to implant doping, for               
            example, to block N+ doping over the field oxide region.  The entire layer is then              
            doped, for example, with P type dopant after removal of the doping barrier.  The                
            second doping results in formation of a high resistivity resistor over the field oxide          
            region, without affecting the transistor gate.  Contact regions are then formed of an           
            appropriate material, for example a silicide, for connecting the resistor to other              
            devices.                                                                                        
                   Claims 1 and 14 are representative of the claimed invention and are                      
            reproduced as follows:                                                                          
                   1. A method comprising steps of:                                                         
                   forming a layer over a transistor gate region and a field oxide region, said             
            transistor gate region being situated over a well and said field oxide region not               
            being situated over said well, wherein said field oxide region and said well are                
            situated in a substrate;                                                                        
                                                     2                                                      



Page:  Previous  1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  Next

Last modified: September 9, 2013